1. Field of the Invention
This invention relates to a memory system for a computer which includes an array of RIMMs (Rambus Interface Memory Modules), time delay elements on the clock lines for the RIMMs, and a time delay element on the clock line for the motherboard on which the array of s are interconnected so as to allow the timing of clock signals to be adjusted independently from the timing of data signals with the advantage of allowing a relatively large number of memory modules to be located on the motherboard.
2. Background Art
Computer memory technology is available from Rambus, Inc. which incorporates arrays of memory modules known commercially as RIMMs (Rambus Interface Memory Modules). Such memory modules consist of chips known as RDRAMs (Rambus dynamic random access memories). Prior to the advent of the aforementioned RIMM memory module, memory speeds were limited to about 100 MHz. The ability to increase the speeds of CPUs in the computer field was hampered by the relatively slow memory speeds. However, RIMM memory modules are now capable of running at speeds of about 400 MHz which is more compatible with current CPU speeds.
Nevertheless, there exists an inherent timing limitation with conventional RIMM memory modules which can effect their reliability (e.g. as a consequence of noise, signal distortion, and the like) as well as the number of such modules that can be adequately supported on a motherboard and the number of applications that can be successfully performed thereby. More particularly, FIG. 1 of the drawings illustrates a conventional RIMM memory module 1 comprising a plurality of RDRAM memory elements 2-1, 2-2 . . . 2-N. Each memory element of the memory module 1 has respective contact pins that are connected at the system level to a plurality of signal paths including an address line (ADRS), a data bus line (DATA), a clock-from-master line (CFM), and a clock-to-master line (CTM).
Turning now to FIG. 2 of the drawings, there is shown a data eye diagram which is characteristic of the Rambus RIMM technology shown in FIG. 1. In this regard, there are three timing parameters that affect the performance of the standard Rambus channel:
TQ: timing skew between clock and data
TR: setup and hold time of the receiver (or input buffer)
ISI: channel intersymbol interference.
These parameters are related according to the following expression:
TQ+TR+ISI less than T/2;
where T is the bit period.
The ideal time to sample data transmitted on the data line would be at the center of the data pulse (designated t0 in FIG. 2). However, it may be appreciated that the clock pulse CL in FIG. 2 is generated leading to the left and lagging to the right of the center time line t0. With the clock pulse leading to the left of time line t0 (as shown), the timing skew TQ is a negative number. However, with the clock pulse lagging to the right of time line t0, the timing skew will be positive.
At 800 Mbps, typical values of the aforementioned parameters (T=1,250 psec) are:
TQ=300 psec max
TR=200 psec max
ISI=125 psec max (for 3 memory slots)
Among these three parameters, TQ can be adjusted at the module level. TR is set by the receiver (input buffer) of the RDRAMs. ISI is set by the number of modules and the number of RDRAM devices per module. That is to say, ISI increases as more modules are placed on the Rambus motherboard.
There is a need in the industry to increase the number of memory modules that can be placed on the motherboard. This provides flexibility in upgrading the system memory as the need arises. In order to increase the number of modules on a Rambus based system, the parameters TQ and TR would have to be made smaller as the third parameter ISI increases with the number of modules. Since the parameter TR is set by the receiver and can not be controlled, it would be desirable to have available a relatively simple and accurate method to reduce the parameter TQ so as to overcome the timing limitation at both the Row module level and the system (motherboard) level.
In general terms, an improved Rambus memory system is disclosed for use in a personal computer. Each RIMM (Rambus Interface Memory Module) includes a plurality of RDRAMs that are selected so as to have substantially similar timing skews (TQ) between clock and data pulses. Each RDRAM is coupled to a plurality of signal paths including an address line, a data bus line, a clock from master (CFM) line, and a clock to master (CTM) line. According to the improvement of this invention on a module level, a first module time delay element is located in the CTM clock line at the output port thereof. A complementary module time delay element is also located in the CTM clock line at the input port. Either time delay can be positive or negative provided that the sum of the first and complementary module time delays equals 0.
A series of RIMMs are located on a motherboard and coupled to a chipset (i.e. memory controller) to which the address line, data bus line, and CFM and CTM clock lines are connected. According to the improvement of this invention on a system level, a positive or negative system time delay element is located in the CFM clock line at the input port thereof. Each of the module and system time delays herein disclosed can be implemented by making the CFM or CTM line traces shorter or longer than the data bus line trace.
By virtue of the foregoing, the clock timing can be adjusted from the data timing. Therefore, the overall system TQ can be reduced so as to provide larger timing margins in the TQ, TR and ISI parameters of the Rambus channel and greater tolerance against error. Accordingly, the Rambus system is made more reliable, whereby the motherboard can support a larger number of RIMMS to accomplish a wider variety of applications. Thus, the robustness of a conventional Rambus system may be increased.